In general, a MTCMOS refers to a structure in which MOS switches with relatively high threshold voltages (high-Vth) are serially connected between a power source and a logic circuit. To reduce power consumption, power may be connected to or disconnected from the logic circuit (including MOS transistors with a relatively low threshold voltage) by turning on or off MOS switches.
FIG. 1A illustrates the structure of a MTCMOS cell 100. FIG. 1B illustrates the structure of a MTCMOS cell 110 in which high-Vth transistors 104 and 106 are inserted into the upper and lower ends of the CMOS cell 102 so that current flow can be stopped in sleep mode. Referring to FIG. 1B, a PMOS transistor 104 inserted into the upper end of the CMOS cell 102 is referred to as a header. An NMOS transistor 106 inserted into the lower end of the CMOS cell 102 is referred to as a footer. A virtual VDD line is connected between the header 104 and the CMOS cell 102 and a virtual ground (GND) is connected between the footer 106 and the CMOS cell 102. Therefore, in sleep mode, due to the high threshold voltage of the footer 104, leakage current can be effectively broken.
FIG. 2 illustrates the layout of the MTCMOS cell 110 of FIG. 1. FIG. 2 illustrates an example of using NMOS transistor 202 as the footer. As illustrated in FIG. 2, in the MTCMOS cell 110, two kinds of transistors 200 and 202 with a low threshold voltage Low-Vth and a high threshold voltage High-Vth are used. To increase speed, transistor 200, with a low threshold voltage, is used, since the MTCMOS cell for switching a signal needs to operate at high speed. To reduce leakage current, footer transistor 202, with a high threshold voltage, is used as a cutoff switch. In this layout of the MTCMOS cell 110, pick-up cells including N+ and P+ implants together with the MTCMOS cell 110 are required.
FIG. 3 illustrates the placement of a MTCMOS cell 304 and pick-up cells 300 and 302 in the layout of MTCMOS. In the layout of the MTCMOS, as illustrated in FIG. 3, the MTCMOS cell 304 without having any pick-up and the pick-up cells 300 and 302 consisting of the pick-up only are adjacent to each other and connected to each other. In order to effectively supply the power source to the cells 304, the pick-up cells 300 and 302 are commonly placed to be separated from the MTCMOS cell 304 by the distance of 50 μm. In FIG. 3, a reference numeral represents a power line in PMOS area of the MTCMOS cell 304.
FIG. 4 is a sectional view taken along a power line 306 in PMOS area of the MTCMOS cell 304 without the pick-up in FIG. 3 in a horizontal direction, in which the pick-up cells 300 and 302 are positioned on both sides of the MTCMOS cell 304. In this regard, as illustrated in FIG. 4, the pick-up cells 300 and 302 have only N+ in the end of the PMOS area. Since the MTCMOS cell 304 does not have N+, the MTCMOS cell 304 must be used together with the pick-up cells 300 and 302. In FIG. 4, a reference numeral 404 refers to a contact and a reference numeral 404 refers to a metal line.
That is, in the layout of the related MTCMOS, it is necessary to separate the MTCMOS cell and the pick-up cells from each other by the distance of 50 μm, which hinders an effective placement of the MTCMOS cell and the pick-up cells. Further, such an MTCMOS architecture needs to use additional pick-up cells so that the space of the semiconductor substrate is unnecessarily wasted.